(1) Field of the Invention
The present invention relates to arithmetic decoding apparatuses and methods, and particularly to an arithmetic decoding apparatus and method for decoding coded data with regard to H.264/AVC video.
(2) Description of the Related Art
Along with the development of digital technology, technology for coding image information is also evolving and developing. With this, the data amount for image information, particularly video information, also becomes extremely large. As such, when coded data of digital images is broadcast or transferred using media such as a Digital Versatile Disc (DVD), the transfer amount becomes extremely large. In particular, the data amount for hi-vision broadcasts and the like, which have recently come into practical use, assumes a size that is 6 times that of the data amount for conventional Standard Definition (SD) images.
Along with the development of digital image technology, technology for compressing data in order to process the increasing data amount is developing. Such development is being realized through compression technology which takes advantage of the attributes of image data. Furthermore, along with the enhancement of the information processing performance of computers, complex arithmetic operations required by compression technology has become possible and the compression ratio for image data is improving significantly. For example, there is the compression technique called MPEG-2 which is adopted by satellite digital hi-vision broadcasts or terrestrial digital hi-vision broadcasts. With MPEG-2, image data of a satellite digital hi-vision broadcast can be compressed to approximately 1/30th of the original size.
AVC/H.264 (H.264/AVC) has been standardized as the next image compression technique following MPEG-2. AVC/H.264 is a standard which realizes a compression ratio that is approximately twice that of MPEG-2. AVC/H.264 realizes a high compression ratio by implementing and combining a number of compression techniques. Consequently, the amount of arithmetic operations required by compression techniques such as AVC/H.264 also increases significantly.
As one compression technique implemented in AVC/H.264, there is entropy coding (variable-length coding). The two methods, CAVLC and CABAC, are provided as entropy coding methods. CAVLC stands for Context Adaptive Variable Length Coding, and is a method of coding in which, in the coding of a DCT coefficient, the run and the level, which are lengths of successive 0s, are coded starting from the direction opposite the scanning direction, using a variable length coding table.
CABAC stands for Context-based Adaptive Binary Arithmetic Coding and is a method of coding in which the appearance frequency of a coding target which varies with time is changed.
Furthermore, CABAC is a method generally referred to as arithmetic coding. In CABAC, in addition to ordinary arithmetic coding, a context index (hereafter denoted as ctxIdx) is assigned to each code to be compressed, and changes to, and management of, the appearance frequency is performed for each of the ctxIdx.
In CABAC, coding is mainly divided into two processes. The first process is called binarization and is for converting, into binary data, multivalue information to be coded that is called a syntax element. The second process is a process for performing arithmetic coding by calculating a context index (ctxIdx) with respect to the binary data obtained in the binarization.
Here, the binary data in arithmetic coding is classified according to syntax element or neighboring macroblock information, and the context index refers to the identification number assigned to each classification.
The process for decoding data coded using CABAC (hereafter denoted as “coded data”) is mainly divided into two processes in the same manner as in the above-described coding. These are: a process of performing arithmetic decoding on coded data and outputting binary data; and a process of multivaluation in which the binary data is converted into a syntax element.
Arithmetic decoding is performed according to the procedure below.
1. Syntax element and binIdx are inputted to the decoding circuit (unit). In the arithmetic decoding, 1-bit binary data (binVal) corresponding to the inputted syntax element and binIdx is outputted in one process. Here, binVal is a value of binary data, and binIdx is information specifying the location of binary data in a sequence of binary data making up multivalue information.
2. A context index is calculated by performing an arithmetic operation using the syntax element, the binIdx, and neighboring macroblock information.
3. A probability variable table is accessed using the calculated context index, and pStateIdx, which is an occurrence probability currently assigned to the context index, and vaIMPS, which is information representing a high occurrence probability symbol, are read.
Here, the vaIMPS is a value of the Most Probable Symbol (MPS), that is, a value of a symbol having the highest occurrence probability. Furthermore, the pStateIdx is the number of the table having the occurrence probability of the MPS, from which the corresponding MPS occurrence probability can be obtained.
4. An arithmetic operation is performed with the pStateIdx and the vaIMPS as input, together with codIRange and codIOffset which are interval information used in arithmetic coding, and 1 bit of binary data is outputted.
5. The codIRange and the codIOffset are updated.
6. The occurrence probability pStateIdx and vaIMPS are updated, and the value of the occurrence variable table is updated.
7. The values of the next syntax element and binIdx are determined. The values of the next syntax element and binIdx is calculated using the decoded binVal (binary data), and the decoding process is completed. The syntax element and binIdx calculated here become the inputs in the decoding of the next binVal.
However, the above-described procedure for arithmetic decoding requires a long processing time, and there is the problem that high-speed arithmetic decoding is not possible.
In the arithmetic decoding procedure, much processing time is mainly required in the following 4 processes. These are specifically: 1) calculating the context index; 2) reading the pStatIdx/vaIMPS from the probability variable table; 3) calculating the binVal (binary data) using the codIRange and codIOffset; and 4) calculating the next syntax element and binIdx.
In addition, in order to output the 1-bit binVal, it is necessary to perform the above-mentioned 4 processes 1) to 4). Furthermore, all these 4 processes cannot be executed unless the immediately preceding process is completed.
One method for solving such problem is disclosed in Japanese Unexamined Patent Application Publication No. 2001-189661 (Patent Reference 1). In the decoding apparatus in the aforementioned Patent Reference 1, processing is performed in advance for each of an immediately subsequent symbol, a 2nd subsequent symbol, and a 3rd subsequent symbol, and information corresponding to each situation that can actually be obtained is outputted in parallel. Subsequently, a selector is controlled and one of the parallelly outputted information is selected using the actual decoding result.
The decoding apparatus in the aforementioned Patent Reference 1 generates 4 contexts using a context generator and reads the values corresponding to the contexts from 4 context RAMs.
Furthermore, the problem of a hazard occurring in a pipeline following the updating of the probability variable is handled by providing the LPS and MPS of probability variables for the case where the contexts are the same. With this, high-speed arithmetic decoding is realized.
However, in the decoding apparatus in the aforementioned Patent Reference 1, the syntax element covered by CABAC is not defined, and thus CABAC is not taken into consideration. As such, high-speed arithmetic decoding using CABAC is not realized.